ICS8633-01 Datasheet | Integrated Circuit Systems

DESCRIPTION The ICS8633-01 is a high performance 1-to-3 Differential-to-3.3V LVPECL Zero Delay Buffer Hi Per Clock S™ and a member of the Hi Per Clock S™ family of High Performance Clock Solutions from ICS. The ICS8633-01 has two selectable clock inputs. The CLKx, n CLKx pairs can accept most standard differential input levels. Utilizing one of the outputs as feedback to the PLL, output frequencies up to 700MHz can be regenerated with zero delay with respect to the input. Dual reference clock inputs support redundant clock or multiple reference applications. FEATURES - Three differential 3.3V LVPECL outputs - Selectable differential clock inputs - CLKx, n CLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL - Output frequency range: 31.25MHz to 700MHz - Input frequency range: 31.25MHz to 700MHz - VCO range: 250MHz to 700MHz - External feedback for “zero delay” clock regeneration - Cycle-to-cycle jitter: 25ps (maximum) - Output skew: 25ps (maximum) - PLL reference zero delay: 50ps ± 100ps - 3.3V operating supply - 0°C to 70°C ambient operating temperature - Industrial temperature information available upon request - Available in both standard and lead-free Ro Hs-pliant packages IC S BLOCK DIAGRAM PLL_SEL ÷4, ÷8 0 1 1 Q2 n Q2 Q0 n Q0 0 Q1 n Q1 PIN ASSIGNMENT PLL_SEL VCC SEL0 SEL1 CLK0 n CLK0 CLK1 n CLK1 CLK_SEL MR VCC n FB_IN FB_IN VEE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCCA VEE VEE VCCO VCCO Q2 n Q2 Q1 n Q1 Vcco Vcco Q0 n Q0 VEE CLK0 n CLK0 CLK1 n CLK1 CLK_SEL FB_IN n FB_IN SEL0 SEL1 MR 28-Lead, 209-MIL SSOP 5.3mm x 10.2mm x 1.75mm body package F Package Top View 8633AF-01 .icst./products/hiperclocks.html REV. A JANUARY 26, 2006 Integrated Circuit Systems, Inc. .. 1-TO-3 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY BUFFER TABLE 1. PIN DESCRIPTIONS Number 1 2, 11 3 4 5 6 7 8 9 Name PLL_SEL VCC SEL0 SEL1 CLK0 n CLK0 CLK1 n CLK1 CLK_SEL Input Power Input Input Input Input...